In FIG. 1, a schematic diagram of a conventional phase locked loop 100 is illustrated. Referring to this figure, a well known phase detector and charge pump 102 typically includes a digital phase detector and a "tri-state" charge pump, such as the ones illustrated in FIGS. 2A and 2B, respectively.
Referring to FIGS. 2A and 2B, the phase detector compares the phase P.sub.i of an input signal against the phase P.sub.f of a feedback signal. If P.sub.f lags P.sub.i, the phase detector outputs a logic 0 at .mu.-not. If P.sub.f leads P.sub.i, the phase detector outputs a logic 0 at D-not. If P.sub.f and P.sub.i are in phase, U-not and D-not are both high. A logic 0 at .mu.-not turns on transistor 202, which in turn activates a constant current source that includes resistors 204-206, diode 208 and transistor 210. When activated, this current source causes a constant positive current of magnitude I.sub.peak to flow from the output of the charge pump into a loop filter 104. Similarly, a logic 0 at D-not turns on transistor 212 which in turn activates a constant current sink that includes resistors 214-216, diode 218 and transistor 220. This current sink causes a constant negative current of magnitude I.sub.peak to flow from loop filter 104 back into the charge pump.
A suitable linear model or transfer function for phase detector/charge pump 102 is: EQU I.sub.p /P.sub.e =K.sub.p ( 1),
wherein P.sub.e is the phase error (P.sub.i -P.sub.f) and K.sub.p is the gain factor for phase detector/charge pump 102. K.sub.p is directly proportional to the magnitude I.sub.peak of the current sourced and sinked by the charge pump. (It should be noted that the transfer function for the phase detector/charge pump is not entirely correct. The equation requires that the amplitude of the output current be directly proportional to the phase error P.sub.e, but the actual output of the phase detector/charge pump is current pulses of constant amplitude I.sub.peak. However, the duration of the pulses is proportional to the phase error P.sub.e. As will be described below, the filter 104 integrates the output current I.sub.p to produce the error voltage V.sub.e. Since the filter integrates the current I.sub.p, the error voltage output V.sub.e predicted by the mathematical model will be substantially the same as the actual error voltage.)
Returning to FIG. 1, the loop filter 104 includes a capacitor which integrates the output current I.sub.p, and a resistor R, which affects the dynamic characteristics of the phase locked loop, in particular the damping factor. The output of filter 104 is an error voltage V.sub.e which is coupled to the input of the voltage controlled oscillator (VCO) 106. In the Laplace domain, the transfer function for loop filter 104 is: EQU V.sub.e /I.sub.p =R+1/Cs (2).
The output frequency of VCO 106 is directly proportional to the input error voltage V.sub.e : EQU W.sub.o =K.sub.v V.sub.e ( 3),
wherein W.sub.o is the radian frequency output and K.sub.v is the gain factor for VCO 106. In the mathematical analysis of phase locked loops, however, we are interested in the instantaneous phase P.sub.o of the output signal. Since frequency is the derivative of phase (W=dP/dt, or, in the Laplace domain, W=sP), the transfer function for the VCO is: EQU P.sub.o /V.sub.e =K.sub.v /s (4).
In FIG. 3A, the output current I.sub.p of phase detector/charge pump 102 is illustrated graphically for the situation in which the phase locked loop is initially out of lock and the phase P.sub.f of the feedback signal lags the phase P.sub.i of the input signal. Referring to this figure, a series of current pulses 302-305 of magnitude I.sub.peak occur periodically as the loop attempts to lock. Before the loop locks, an overshoot occurs which is represented by a negative current pulse 306. The error voltage V.sub.e at the input of VCO 106 is the sum of the voltage V.sub.c across capacitor C and the voltage V.sub.r across resistor R. These voltages are illustrated respectively in FIGS. 3B and 3C. Voltage V.sub.c is the integral of the current I.sub.p and consequently "ramps up" at 308-311 and "ramps down" at 312. In between these current pulses 302-306, the output current I.sub.p of phase detector/charge pump 102 goes to zero and the output impedance goes to infinity. Thus, assuming that the input impedance of the VCO is also infinite, the voltage V.sub.c that is present at the end of each current pulse 302-306 is held constant by capacitor C. Since the voltage across a resistor is simply the product of the current and the resistance, voltage pulses 314-317 occur simultaneously with current pulses 302-306 and have a magnitude of I.sub.peak R. V.sub.e is illustrated graphically in FIG. 3D. Since V.sub.e is the sum of the voltages V.sub.c and V.sub.r, V.sub.e includes voltage "spikes" 320-324 which are primarily the result of the voltage pulses 314-318 that develop across resistor R.
One of the primary applications for phase locked loops is in frequency synthesizers. The typical frequency synthesizer includes the circuit of FIG. 1 plus a programmable divider inserted between the output of VCO 106 and the feedback input of phase detector/charge pump 102. The divider has been eliminated from FIG. 1 because its presence would not effect the mathematical analysis of the present invention. (Without the divider, P.sub.f =P.sub.o, as illustrated in FIG. 1). A multiplicity of frequencies can be synthesized with such a circuit simply by programming the variable divider to divide by different numbers. Unfortunately, every time the divider is reprogrammed, the phase locked loop unlocks momentarily causing undesirable spurious frequencies to be generated at the VCO output as the VCO tracks the voltage spikes 320-324 at the VCO input. Even when the loop is locked, minor phase corrections are still necessary and current pulses periodically appear at the output of phase detector/charge pump 102, resulting in spurious VCO frequencies.
In the design of frequency synthesizers, it is often desirable to increase the lock time of the loop, that is, to decrease the time between a change in the variable divider and the time the phase locked loop recovers phase lock. As a general rule, this time will be inversely proportional to the "natural frequency" of the loop. The closed loop transfer function for the phase locked loop is: ##EQU1##
From control theory, we know that the denominator of a second order equation can be placed in the following form: EQU s.sup.2 +2dW.sub.n s+W.sub.n.sup.2 ( 6).
wherein d is the damping factor and W.sub.n is the natural frequency. Equating the denominator of the first equation with the second equation we get: ##EQU2##
The natural frequency of the loop can be increased by a factor of n while maintaining the damping factor constant if the magnitude I.sub.peak of the output current I.sub.p (which is directly proportional to K.sub.p) of the phase detector/charge pump 102 is increased by a factor of n.sup.2, while the resistance R is decreased by a factor of n. In other words, if n.sup.2 K.sub.p is substituted for K.sub.p, and R/n is substituted for R in the two equations immediately above, W.sub.n will be n times larger than it was before, but d remains the same.
Unfortunately, there are practical limitations to this technique for decreasing lock time. The undesirable voltage spikes 320-324 that develop across resistor R, would be larger by a factor of n if the magnitude I.sub.peak of the output current I.sub.p were to be increased by n.sup.2 while only reducing R by a factor of n. This would not only increase the spurious frequency output of the VCO, but would also cause the circuit to exceed dynamic range limitations. For example, if a phase locked loop is designed such that the voltage pulses 314-318 developed across resistor R are .+-.5 Volts and the available power supply voltage is .+-.10 Volts, and if it is desired to decrease lock time by a factor of 10 (by increasing the output current I.sub.p by 10.sup.2 and decreasing resistance R by 10), the theoretical peak voltage developed across resistor R would be .+-.50 Volts. But .+-.50 Volts is beyond the limits of the power supply. Consequently, such an attempt at decreasing lock time would fail and result in the introduction of severe non-linearities into the circuit.
Accordingly, the invention described below eliminates the resistor R from the loop (i.e., a resistor-less or ideal integration loop), but maintains the dynamic characteristics (e.g., damping factor) of the conventional loop. Thus, the natural frequency W.sub.n of the loop may be increased (thereby decreasing lock time) without the spurious frequencies and potential non-linear circuit problems caused by the resistor R in the conventional loop.
Before describing the preferred embodiment of the invention it will be helpful to develop a mathematical model of the conventional phase locked loop so that a comparison can be made between the mathematical model of the present invention and the mathematical model of the conventional loop. Although the closed loop equation has already been described, the open loop equation is also indicative of loop performance and is generally easier to deal with. The open loop equation for the conventional phase locked loop is simply the multiplication of the transfer functions for the phase detector/charge pump 102, the loop filter 104 and the VCO 106, and it can be written in the following form: EQU P.sub.f /P.sub.e =(K.sub.p R+K.sub.p /Cs)(K.sub.v /s) (9).
A graphical model of the open loop equation of the conventional phase locked loop is illustrated in FIG. 4.